Critical Race Example

With the delays reversed (Y0’ delay 3ns and Y1’ delay 2ns) the circuit works as expected.

architecture race_example2 of EIQ is

signal y1, y0 : std_logic;

begin

y1 <= (y1 and enable) or (i and enable and (not y0)) after 2 ns;

y0 <= i or (y1 and enable) after 3 ns;

q <= y1;

end race_example2;