Critical Race Example

Unfortunately this state assignment suffers from a critical race condition. This can be demonstrated via a VHDL simulation, with the next state equations given arbitrary delays.

library ieee;

use ieee.std_logic_1164.all;

entity EIQ is

port (i, enable : in std_logic;

q : out std_logic);

end EIQ;

architecture race_example1 of EIQ is

signal y1, y0 : std_logic;

begin

y1 <= (y1 and enable) or (i and enable and (not y0)) after 3 ns;

y0 <= i or (y1 and enable) after 2 ns;

q <= y1;

end race_example1;

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