CSE21COR (Computer Organisation) : Digital Logic
Assignment Hints

Lecturer: Geoffrey Tobin

• Further explanations for question 1: why parallel load doesn't overwrite bit D0, and how the extra flip-flop helps.
• Updated hints for counter in question 3: state table and diagram, with an example.

Remember, the CSE21COR assignment is due at:
9 am on Monday 17 May 1999.

* Assignment Hints *

(This information will be updated, so please revisit occasionally.)

Question 1: Five (5) bit Parallel to Serial Converter

Brain teaser:
• The question asks us to load parallel data, which is one operation, and to shift five bits out serially, which is five operations, making six operations, and to do so every five clock cycles. This presents a problem: how do we perform six (6) operations in five (5) clock cycles?

Parallel Load operation:

• Refer to the notes for Lecture 5, page 2, under the heading Data Transfer for an asynchronous parallel load circuit. This method frees the D and Q signals for use in the shift register.
• Note: In the same circuit, there should not be a bar over the PL symbol, because the parallel load signal is active high.

Clock (CLK):

• The clock should be synchronous (the same clock signal should go to the CLK input of every flip-flop in your entire design).

Reset:

• Reset will occur only once, to initialise the converter.
• Modify the design of the parallel load circuitry to allow the Reset signal through to the Clear inputs of the flip-flops. This requires one additional gate for each flip flop in the register.

Counter:

• Since the Parallel Load (PL) signal is to occur every five clock cycles, it needs to be generated using a mod 5 counter.
• Should the counter be synchronous or asynchronous? Why? In what situation is this important? In assignment question 1, does it matter? Why?
• According to the timing diagram below, the parallel load (PL) signal should be generated during counter state 001. Use logic gates to detect this state and to generate an active high signal which we'll call PL1.
• Under the conditions of the question, the PL signal should be active only when the Clock is high. This requires that the PL1 signal generated from the counter be ANDed with the Clock signal to create PL.

Flip Flops:

• The five flip flops of the shift register, and the one extra flip flop, may be of any clocked type, but I recommend D type flip flops as the simplest.
• Should the extra (sixth) flip-flop be placed before, or after, the parallel load section of the shift register?
• Testing your design: To make sure that your design satisfies the specifications of the assignment question, I recommend that you draw a timing diagram for these three signals:
  • CLK
  • Reset (active low)
  • PL (Parallel Load) (active high)
  
  and label the timing diagram with all of the converter's operations (each shift and load) for at least one and a half full sequences from when the Reset occurs.



• Official Timing Diagram:
• If your circuit has a different timing diagram, and doesn't work (for example if the parallel load clobbers one of the data bits before it is output), and you don't know how to correct it, then please promptly make an appointment to see Geoffrey Tobin to discuss your design.
• Important explanation: How do we avoid clobbering the last bit out (D0), given that the parallel load occurs at the same clock edge as the D0 shift? And how does the extra flip-flop help with that?

  Answer:

  • Although the question says to ignore propagation delays setup and hold times, this actually means only to assume that they are all very brief compared to the clock period.
  • Suppose the clock runs at 1 MHz, so the period is 1 microsecond, that is 1000 ns. Propagation delays of 10 ns per gate are indeed small compared to that.
  • Flip flops require a setup time that's large compared to propagation delays. So the data being shifted must be valid for quite a while before the rising clock edge occurs. Since the Q output of each flip flop is stable for one clock period, and this is the D input of the next flip flop, that's ample setup time.
  • However, what you may not know is that the hold time for flip flops is much briefer than gate propagation time. So when the rising edge occurs, D0 is shifted and stored in the extra flip flop almost instantly (in a fraction of a nanosecond). Whereas the PL signal emerges at least one AND gate propagation delay (10 ns) after the clock goes high. So by the time the new data is parallel loaded, the last bit of the old data, D0, is safely stored in the extra flip flop.
  • The extra flip flop changes state only on the rising clock edge, so it which ensures that all the bits output on the serial line, including D0, are valid for almost a whole clock cycle. Therefore the equipment that receives the data at the other end of the serial line can easily synchronise its operation to that of the parallel to serial converter.

    Without the extra flip flop, the serial data might be valid only briefly, which would be make the receiving equipment very susceptible to errors due to tiny variations in timing.

• Block Diagram for one possible solution:

  

Question 2: Timing Diagram for a NAND, OR, XOR circuit.

• In the partial timing diagram given, the X, Y and Z signals are drawn as starting with values 1, 0 and 0 respectively. As observant students have pointed out, this is not correct. Y and the output Z should start as 1 (high).

Question 3: States of an Asynchronous Counter.

• There should not be a bar over the "Clear" labels on the JK flip flops.
• This counter has both clocked (Clock) and combinational (NAND) controls. The clock causes the counter's state to change at regular intervals, but the combinational cause sudden transitions. To distinguish the two types of transition, I strongly recommend that you use a solid arrow for clocked (regular) transitions, and a dashed arrow for the combinational (sudden) transitions.

  This arrow convention can be used in both the table and the state diagram.

• Some of the states of the counter are wanted, while others are unwanted. Among the unwanted states some are stable (they change only with the clock), while others are unstable (they change almost immediately, due to the combinational logic). It's up to you to identify which states fall into each of the three categories: wanted, stable unwanted, and unstable unwanted.

  Incidentally, how does the counter reach unwanted states? Once it's in one of the desired states, it is designed to cycle through them, never reaching any of the unwanted ones. However, what happens when the power is first switched on? The counter could be in any state then. Another way this can happen is if the power flickers momentarily, as occasionally happens to both mains and batteries. A third possibility is that we might try to run the clock too fast: overclocking can cause hardware to enter unwanted states. On PCs, overclocking can cause spontaneous reboots and other unpleasant events.

• In the table, if the Current State is unstable, then precede the Next State by a dashed arrow. For example:

  --> yyyy

  If the Next State is unstable, then follow it by a dashed arrow, then the state that it immediately changes into. For instance:

  yyyy --> zzzz

• Here's a strong hint comprising an example of how you can format your state table to indicate both the clocked and the gated transitions. If we delete bit 0, we obtain a 3-bit mod 5 counter that has the following state table.

  Current State	Next State
  000	001
  001	010
  010	011
  011	100
  100	101 --> 000
  101	--> 000
  110	111 --> 000
  111	--> 000

  In this example, the first five states (000 to 100) are stable, but the next active clock edge causes 100 to transition to an unstable state 101 which the gate logic quickly replaces by 000. States 101 to 111 are unwanted states, but on power-up the counter could start in any state. Normally we'd want the counter to be initialised as zero (here 000), but we haven't provided any initialisation circuitry. Of the three unwanted states, 110 is stable, but 101 and 111 are unstable because of the NAND gate.

  Here's the state diagram for the mod 5 counter. Note which transitions are clocked (synchronous), and which are gated (asynchronous).